*/
// *******************************************************************************
// Company: Fpga Publish
// Engineer: FP 
// 
// Create Date: 2024/03/24 12:39:43
// Design Name: 
// Module Name: verilog_demo
// Project Name: 
// Target Devices: ZYNQ7010 | XCZU2CG | Kintex7
// Tool Versions: 2021.1 || 2022.2
// Description: 
//         * 
// Dependencies: 
//         * 
// Revision: 0.01 
// Revision 0.01 - File Created
// Additional Comments:
// 
// *******************************************************************************
module verilog_demo #(
    //mode
    parameter MD_SIM_ABLE = 0,
    //number
    parameter NB_DELAY_CLK = 100,
    //width
    parameter WD_ERR_INFO = 4
   )(
    //! system signals
    input           i_sys_clk   ,  
    input           i_sys_resetn,  
    //! @virtualbus uart_interface @dir out
    output          m_uart_0_mtx, //! uart master tx
    input           m_uart_0_mrx, //! uart master rx
    //! @end 
    //! error info feedback
    output   [WD_ERR_INFO-1:0]  m_err_verilog_info1
);
//========================================================
//function to math and logic
function automatic integer LOG2(input integer N);
begin
    N = N - 1;
    for(LOG2 = 0; N > 0; LOG2 = LOG2 + 1)
    begin
        N = N >> 1;
    end
end 
endfunction

//========================================================
//localparam to converation and calculate

//========================================================
//register and wire to time sequence and combine

//========================================================
//always and assign to drive logic and connect

//========================================================
//module and task to build part of system

//========================================================
//expand and plug-in part with version 

//========================================================
//ila and vio to debug and monitor

endmodule
              
/* end verilog