Modify DDR frequency on MDM9x07 platform

For MDM9x07, the supported clock plan table can be found in

rpm_proc\core\systemdrivers\clock\config\mdm9x07\ClockBSP.c.

const ClockMuxConfigType BIMCClockConfig[]

{

{ 9600000, { HAL_CLK_SOURCE_XO, 1, 0, 0, 0 },

CLOCK_VREG_LEVEL_LOW },

{ 48000000, { HAL_CLK_SOURCE_GPLL2, 10, 0, 0, 0 },

CLOCK_VREG_LEVEL_LOW },

{ 96000000, { HAL_CLK_SOURCE_GPLL2, 5, 0, 0, 0 },

CLOCK_VREG_LEVEL_LOW },

{ 120000000, { HAL_CLK_SOURCE_GPLL2, 4, 0, 0, 0 },

CLOCK_VREG_LEVEL_LOW },

{150150000, { HAL_CLK_SOURCE_BIMCPLL, 4, 0, 0, 0 },

CLOCK_VREG_LEVEL_LOW_PLUS },

{ 240000000, { HAL_CLK_SOURCE_GPLL2, 2, 0, 0, 0 },

CLOCK_VREG_LEVEL_NOMINAL },

{ 300300000, { HAL_CLK_SOURCE_BIMCPLL, 2, 0, 0, 0 },

CLOCK_VREG_LEVEL_HIGH },

{ 0 }

};

8.1.1 Limit DDR frequency (Fmax)

The following example codes show how to set Fmax to the next lower frequency.

Locate RPM build and open “core/systemdrivers/clock/hw/mdm9x07/ClockRPM.c” file

void Clock_BusSetMinMax( Clock_NPAResourcesType *pNPAResources )

{

/* Default setting for BIMC clock */

pNPAResources->BIMCClockResource.nMinLevel = 0;

pNPAResources->BIMCClockResource.nMaxLevel = MAX_LEVEL;

pNPAResources->BIMCClockResource.nMaxLevel = 4; // limit the frequency

level to 4 i.e 300 MHz